The Carbon Nanotubes (CNT) are viewed to be a new key element for future electronics. In the CNT, such unique properties as quantization of the electron spectrum, ballistic electron propagation along the tube, current densities as high as 109 A/cm2, existence of the semiconductor phase, possibilities for n- and p-doping with a high carrier mobilities, as well as excellent thermal conductance, make the nanotubes a great candidate for future novel high-speed, high efficiency electronic and photonic devices.
The key element widely used in the electronic logic circuits is CMOS, wherein both switching states consume minimum energy, see. e.g. J. R. Brews in High-speed Semiconductor Devices, J. Wiley &Sons, New York, p. 139, 1990. It is therefore important for future nanotube applications to reproduce such an element using CNT technology. Such attempts have been carried out in many research places worldwide.
FIG. 1a shows as a Prior Art two CNT FETs in series, with n-type and p-type channel field-effect transistors (FET) forming the CMOS circuit, see V. Derycke et al, Nano Letters 1, p. 453, 2001. The CNT CMOS is made from a single nanotube extended between source and drain metal contacts deposited on the Si substrate, while the controlling gate electrodes are made simply by placing the nanotube on top of the SiO2 insulating layer on the n+Si substrate. To convert originally p-type CNT into n-type, one of the transistors has been subjected to annealing in vacuum. The resultant effect of voltage switch is shown in FIG. 1b. 
The proof-of-concept design, used in the above cited work, where a single nanotube is placed on the substrate between the contacts, is utilized in essentially all publication on this topic, for both CMOS circuit and individual transistors (see also E. Ungersboeck, et al, IEEE Transactions on nanotechnology, V4, p. 533, 2005). The drawback of this method is its impracticality for any scale of circuit integration: placement of multiple identical nanotubes to enhance the output current or to form new circuit elements requires a special micro-manipulator and thus precludes any possibility of IC mass manufacturing. The future success of CNT devices will rely on emergence of a cost efficient manufacturing process that will ensure a high-yield and cost efficiency above the modern CMOS technology.
The present invention discloses this technology. It is based on the growth of a controllable nanotube array on a metal electrode normally to the electrode plane and then sequential deposition of dielectric and metal layers to produce a solid platform for attachment of a second common contact to all the nanotube tips, thereby forming source and drain electrodes. The transistor gate electrode is made as a third conductive layer sandwiched between the dielectric layers and placed somewhere in the middle of the nanotube length.
Such a technology was described in the patent application Ser. No. 11/705,577 filed by A. Kastalsky on February 2007, where several nanotube array devices and method for their fabrication have been disclosed. Shown in FIG. 2 as a Prior Art, is the nanotube array FET (the direction of the nanotube array is normal to the drawing plane) in which the nanotubes are grown normally to the substrate, and the gate electrode 51 is attached to the sidewall of every nanotube 57 in the array through a layer of insulator 54. The key element is the metal layer 51 in the middle of the nanotube length, sandwiched between two insulator layers 52 and 53. During deposition of the first insulator layer 52, a thin layer of insulation material will also be deposited on the nanotube walls, thereby forming a gate insulator layer 54 around each nanotube. It is then followed by deposition of the gate metal layer 51 and the insulator layer 53. After polishing of the insulator layer 53 and exposure of the nanotube tips, the top metal layer 55 (the drain electrode) is deposited to complete the structure. Such a design of the CNT transistor, with the nanotube buried within sequentially deposited insulating and metal layers, allows realization of the planar technology for commercial manufacturing of the CNT-based integration circuits. Several nanotube array devices will be disclosed below, all of them relying on the method of planar multilayer deposition technique combined with the appropriate processing for controllable formation of p- and n-type regions along the nanotube length during the device fabrication.
Simple methods of variation of the carrier type of conductivity along the nanotube, utilized in the disclosed technology, allow simple fabrication of p-n diodes. They are expected to possess an extremely low intrinsic capacitance due to small nanotube diameter and therefore, very high operational frequency. Furthermore, p-n-p or n-p-n structures suitable for manufacturing of bipolar transistors are also within the scope of the disclosed devices.
The electron-hole injection in the forward bias direction will provide inter-band optical emission due to electron-hole radiative recombination. Below, the nanotube array Light Emitting Diodes and Lasers will be disclosed, wherein excellent optical properties of CNTs ensure high efficiency of the proposed optoelectronic devices.
The first object of the present invention is to disclose a new nanotube array circuit, analogous to Si-based CMOS logic element and the processing steps for its fabrication.
The second object of the invention is to disclose the nanotube array bipolar transistor and the technology for its fabrication.
The third object of the invention is to disclose the nanotube array p-n junction injection light emitting diode and the technology for its fabrication.
The forth object of the invention is to disclose the nanotube array injection laser and the technology for its fabrication.